1. Technical Field
Various embodiments relate to a memory controller, and more particularly, to a memory controller and a memory system including the same.
2. Related Art
In order to improve the communication speed between a memory apparatus and a processor such as central processing unit (CPU) or graphics processing unit (GPU), a memory controller or interface chip has been used. Furthermore, a system-in-package (SIP) semiconductor apparatus in which a memory apparatus and a memory controller or interface chip are packaged together has been developed.
Referring to FIG. 1, the memory unit 10 may include a memory bank 11 having a plurality of memory cells to store data. The memory cells MC may be electrically connected to word lines WL0, WL1, and WL2 in a row direction and bit lines BL0, BL1, and BL2 in a column direction (please check them), and located at the respective intersections between the word lines WL0, WL1, and WL2 and the bit lines BL0, BL1, and BL2. The word lines WL0, WL1, and WL2 and the bit lines BL0, BL1, and BL2 may be accessed by a row decoder 12 and a column decoder 13, respectively. The row decoder 12 may access a corresponding word line WL0, WL1, or WL2 according to a row address signal, and the column decoder 13 may access a corresponding bit line BL0, BL1, or BL2 according to a column address.
With the increase in integration-density of the memory apparatus, the number of memory cells has geometrically increased. Accordingly, the numbers of word lines and bit lines have also increased. That is, size of the memory cells, a distance between the word lines WL0, WL1, and WL2, and a distance between the bit lines BL0, BL1, and BL2 have been significantly reduced. Therefore, when specific word lines or bit lines are successively accessed, memory cells electrically connected to an adjacent word line or bit line may be influenced. That is, as the specific word lines or bit lines are successively accessed, data stored in the memory cell connected to the adjacent word line or bit line may be destroyed or varied. Thus, the reliability of the memory cell may be degraded.